Optimizing Data Transport Architectures for Automotive AI, ADAS, and Embedded Vision System-on-Chip (SoC) Architectures

This presentation addresses the challenges and solutions in data transport for automotive AI, ADAS, and embedded vision systems, focusing on Networks-on-Chips (NoCs) in RISC-V and Arm-based SoCs. It highlights the ‘memory wall’ issue and emphasizes NoC implementation’s role in optimizing performance, power efficiency, and cost. Key points include evaluating NoC protocols for adaptability and efficiency in automotive SoCs, introducing frameworks for cache-coherent and non-coherent applications, and emphasizing early assessment of physical design constraints to reduce interconnect area and power usage. The presentation also explores challenges in multiprotocol and cache coherent interconnects and the importance of ISO26262 certification for safety. Integrating Arteris’ NoC solutions with advanced processor architectures is presented as a means to achieve more efficient, flexible, and high-performing automotive SoCs